As part of my Digital System Design course (ECE 341 at ODU), I proposed and independently developed a custom project focused on designing a passive signal detection and processing system. This initiative was taken prior to formal coursework in digital signal processing or control systems and alongside Circuits II and Calculus III, with a foundation primarily in C++.

The project leveraged VHDL within ALDEC Studio and used a publicly available IEEE dataset containing drone communication signals (uplink/downlink across 13 drone types). Signals were preprocessed into an 8-bit format using MATLAB to simulate input acquisition, with the assumption of ideal input signals due to scope constraints.

I implemented a 16-point Radix-4 FFT (Fast Fourier Transform) algorithm for frequency-domain analysis, selecting and adapting a published hardware-oriented FFT structure suitable for VHDL implementation. A key focus outside of the FFT algorithm was on planning and synchronizing the modular components of the system through FSM-based control logic (Finite State Machine), with careful attention to timing and overflow challenges common in hardware design.

This project provided hands-on experience in designing digital systems with modularity and interoperability in mind, and highlighted the importance of system planning prior to implementation.

System Design

The overall system consisted of modular components coordinated by FSM-based control logic. The processing flow was:

1. Detect signal activity
2. Buffer incoming samples
3. Trigger FFT processing
4. Store processed frequency data

Once buffering completed, the system triggered a secondary FFT controller to process 16-sample segments using a hardware-oriented 16-point Radix-4 FFT based on the paper:
“Design of 16-Point Radix-4 Fast Fourier Transform in 0.18 µm CMOS Technology,” Palaniappan, Zulkifli, et al.

I adapted the algorithm for VHDL implementation and addressed challenges including:

• timing misalignment between computation stages
• incorrect twiddle factor application
• index ordering errors and mismatched butterfly pairings
• overflow during intermediate arithmetic

To mitigate these issues, I consolidated several initially separate modules (butterfly operators, twiddle factor lookup, and complex multiplication) into the FFT processor, and introduced additional state transitions to better synchronize computations. Signal resizing and scaling shifts were used to prevent overflow.

The primary system controller monitored FFT completion flags and wrote results to a processed-signal storage module, with multi-cycle delays added to ensure correct write alignment. A persistent counter ensured processed data was always written to new memory locations.

Debugging

A major portion of the effort involved diagnosing timing-related logic errors, such as pointer offsets and mis-indexed memory outputs. I built internal reporting signals and console trace outputs to observe state transitions and intermediate values, which significantly accelerated fault isolation.

Conclusion

Ultimately, a working prototype was obtained though modifications made to the implementation of the system algorithm though is room for improvement to efficiency of the system through use of parallel processing, such as running 8 FFT processing modules in parallel, and refining the modular structure.  This prototype met the requirements of a baseline passive signal collection and processing system and has passed initial testing of functionality.

Key takeaways:

• Designed a simple digital signal processing pipeline in VHDL
• Implemented and adapted a published Radix-4 FFT architecture
• Built FSM-driven control logic for synchronization and flow management
• Solved timing, overflow, and indexing bugs through structured debugging
• Delivered a functional prototype meeting project requirements